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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_hppass_dac_t Struct Reference<div class="ingroups"><a class="el" href="group__group__hppass.html">HPPASS       (High Performance Programmable Analog Sub-System)</a> &raquo; <a class="el" href="group__group__hppass__csg.html">CSG (Comparator Slope Generator)</a> &raquo; <a class="el" href="group__group__hppass__csg__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>The DAC configuration structure. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a2c9a808964eac41a05b14cea5fee14d4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__hppass__csg__enums.html#gaef7316fc8b82f487e96a0d46bc0cba8f">cy_en_hppass_dac_start_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a2c9a808964eac41a05b14cea5fee14d4">start</a></td></tr>
<tr class="memdesc:a2c9a808964eac41a05b14cea5fee14d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC trigger start.  <a href="#a2c9a808964eac41a05b14cea5fee14d4">More...</a><br /></td></tr>
<tr class="separator:a2c9a808964eac41a05b14cea5fee14d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1192918c65df8c3f38d9d0f90b3f8e2d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__hppass__csg__enums.html#ga558d225d23ba6be92114187027040ea1">cy_en_hppass_dac_update_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a1192918c65df8c3f38d9d0f90b3f8e2d">update</a></td></tr>
<tr class="memdesc:a1192918c65df8c3f38d9d0f90b3f8e2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC trigger update.  <a href="#a1192918c65df8c3f38d9d0f90b3f8e2d">More...</a><br /></td></tr>
<tr class="separator:a1192918c65df8c3f38d9d0f90b3f8e2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9809ce5e9ab5f783a4fbcc811ce36865"><td class="memItemLeft" align="right" valign="top"><a id="a9809ce5e9ab5f783a4fbcc811ce36865"></a>
<a class="el" href="group__group__hppass__csg__enums.html#ga0742afc1d240bfd4d092b72b0c47dbac">cy_en_hppass_dac_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865">mode</a></td></tr>
<tr class="memdesc:a9809ce5e9ab5f783a4fbcc811ce36865"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC mode. <br /></td></tr>
<tr class="separator:a9809ce5e9ab5f783a4fbcc811ce36865"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77ddc8b9253d0187c4ee4d7b913d1387"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a77ddc8b9253d0187c4ee4d7b913d1387">continuous</a></td></tr>
<tr class="memdesc:a77ddc8b9253d0187c4ee4d7b913d1387"><td class="mdescLeft">&#160;</td><td class="mdescRight">Continuous mode.  <a href="#a77ddc8b9253d0187c4ee4d7b913d1387">More...</a><br /></td></tr>
<tr class="separator:a77ddc8b9253d0187c4ee4d7b913d1387"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4cf7e8ca9a71c950988411c5fecfb8b6"><td class="memItemLeft" align="right" valign="top"><a id="a4cf7e8ca9a71c950988411c5fecfb8b6"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a4cf7e8ca9a71c950988411c5fecfb8b6">skipTrig</a></td></tr>
<tr class="memdesc:a4cf7e8ca9a71c950988411c5fecfb8b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Skip the first DAC hardware update trigger after the proper <a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865">cy_stc_hppass_dac_t::mode</a> is enabled. <br /></td></tr>
<tr class="separator:a4cf7e8ca9a71c950988411c5fecfb8b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8cc621e33846d40eaa9a313da49a4bb8"><td class="memItemLeft" align="right" valign="top"><a id="a8cc621e33846d40eaa9a313da49a4bb8"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a8cc621e33846d40eaa9a313da49a4bb8">cascade</a></td></tr>
<tr class="memdesc:a8cc621e33846d40eaa9a313da49a4bb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Synchronize parameter update with previous CSG slice in the case of multi-phase operation. <br /></td></tr>
<tr class="separator:a8cc621e33846d40eaa9a313da49a4bb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbdc417fcb0b88013e0a5177f003f1f8"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#afbdc417fcb0b88013e0a5177f003f1f8">paramSync</a></td></tr>
<tr class="memdesc:afbdc417fcb0b88013e0a5177f003f1f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameter Synchronization enable.  <a href="#afbdc417fcb0b88013e0a5177f003f1f8">More...</a><br /></td></tr>
<tr class="separator:afbdc417fcb0b88013e0a5177f003f1f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a815dfa6f4b27d1516d66c8c7df8d1b"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a9a815dfa6f4b27d1516d66c8c7df8d1b">deGlitch</a></td></tr>
<tr class="memdesc:a9a815dfa6f4b27d1516d66c8c7df8d1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC de-glitch time in clock cycles.  <a href="#a9a815dfa6f4b27d1516d66c8c7df8d1b">More...</a><br /></td></tr>
<tr class="separator:a9a815dfa6f4b27d1516d66c8c7df8d1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4d515eeb2978a8d5761ca2b4a975352"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#aa4d515eeb2978a8d5761ca2b4a975352">stepSize</a></td></tr>
<tr class="memdesc:aa4d515eeb2978a8d5761ca2b4a975352"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static value of 6 bit DAC Step Size.  <a href="#aa4d515eeb2978a8d5761ca2b4a975352">More...</a><br /></td></tr>
<tr class="separator:aa4d515eeb2978a8d5761ca2b4a975352"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2737ddc704d45925c4be748eb7daffd1"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a2737ddc704d45925c4be748eb7daffd1">valBuffA</a></td></tr>
<tr class="memdesc:a2737ddc704d45925c4be748eb7daffd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC A value, usage depends on <a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865" title="DAC mode. ">cy_stc_hppass_dac_t::mode</a>.  <a href="#a2737ddc704d45925c4be748eb7daffd1">More...</a><br /></td></tr>
<tr class="separator:a2737ddc704d45925c4be748eb7daffd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b5101273211b56bcb007465522950c6"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#a7b5101273211b56bcb007465522950c6">valBuffB</a></td></tr>
<tr class="memdesc:a7b5101273211b56bcb007465522950c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC B value, usage depends on <a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865" title="DAC mode. ">cy_stc_hppass_dac_t::mode</a>.  <a href="#a7b5101273211b56bcb007465522950c6">More...</a><br /></td></tr>
<tr class="separator:a7b5101273211b56bcb007465522950c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae099986a021a411ecbc5fbb6dd5ee37b"><td class="memItemLeft" align="right" valign="top"><a id="ae099986a021a411ecbc5fbb6dd5ee37b"></a>
<a class="el" href="structcy__stc__hppass__dac__period__t.html">cy_stc_hppass_dac_period_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__hppass__dac__t.html#ae099986a021a411ecbc5fbb6dd5ee37b">period</a></td></tr>
<tr class="memdesc:ae099986a021a411ecbc5fbb6dd5ee37b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DAC Period divider, clocked from CSG clock. <br /></td></tr>
<tr class="separator:ae099986a021a411ecbc5fbb6dd5ee37b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a2c9a808964eac41a05b14cea5fee14d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2c9a808964eac41a05b14cea5fee14d4">&#9670;&nbsp;</a></span>start</h2>

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          <td class="memname"><a class="el" href="group__group__hppass__csg__enums.html#gaef7316fc8b82f487e96a0d46bc0cba8f">cy_en_hppass_dac_start_t</a> cy_stc_hppass_dac_t::start</td>
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<p>DAC trigger start. </p>
<p>If input trigger is selected, it should be in the pulse mode. </p>

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<a id="a1192918c65df8c3f38d9d0f90b3f8e2d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1192918c65df8c3f38d9d0f90b3f8e2d">&#9670;&nbsp;</a></span>update</h2>

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          <td class="memname"><a class="el" href="group__group__hppass__csg__enums.html#ga558d225d23ba6be92114187027040ea1">cy_en_hppass_dac_update_t</a> cy_stc_hppass_dac_t::update</td>
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<p>DAC trigger update. </p>
<p>If input trigger is selected, it should be in the pulse mode </p>

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</div>
<a id="a77ddc8b9253d0187c4ee4d7b913d1387"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a77ddc8b9253d0187c4ee4d7b913d1387">&#9670;&nbsp;</a></span>continuous</h2>

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          <td class="memname">bool cy_stc_hppass_dac_t::continuous</td>
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<p>Continuous mode. </p>
<p>(Only valid for Slope and LUT modes) </p>

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<a id="afbdc417fcb0b88013e0a5177f003f1f8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afbdc417fcb0b88013e0a5177f003f1f8">&#9670;&nbsp;</a></span>paramSync</h2>

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<p>Parameter Synchronization enable. </p>
<p>If set, the DAC parameters will be set only after <a class="el" href="group__group__hppass__csg__dac.html#ga1592d290c2a7c2c30cddaed478555944">Cy_HPPASS_DAC_SetParamSyncReady</a> function call </p>

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<a id="a9a815dfa6f4b27d1516d66c8c7df8d1b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9a815dfa6f4b27d1516d66c8c7df8d1b">&#9670;&nbsp;</a></span>deGlitch</h2>

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          <td class="memname">uint8_t cy_stc_hppass_dac_t::deGlitch</td>
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<p>DAC de-glitch time in clock cycles. </p>
<p>Valid range 0..7 (0 means de-glitching is disabled, 1..7 - de-glitching period in cycles). The de-glitch period should be not grater than the DAC update period. </p>

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<a id="aa4d515eeb2978a8d5761ca2b4a975352"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa4d515eeb2978a8d5761ca2b4a975352">&#9670;&nbsp;</a></span>stepSize</h2>

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<p>Static value of 6 bit DAC Step Size. </p>
<p>Valid range: 1..64 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2737ddc704d45925c4be748eb7daffd1">&#9670;&nbsp;</a></span>valBuffA</h2>

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<p>DAC A value, usage depends on <a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865" title="DAC mode. ">cy_stc_hppass_dac_t::mode</a>. </p>
<ul>
<li>Buffered mode - DAC value</li>
<li>Hysteretic Buffered mode - DAC high threshold</li>
<li>Slope modes - DAC start value</li>
<li>LUT modes - LUT start address </li>
</ul>

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<a id="a7b5101273211b56bcb007465522950c6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7b5101273211b56bcb007465522950c6">&#9670;&nbsp;</a></span>valBuffB</h2>

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<p>DAC B value, usage depends on <a class="el" href="structcy__stc__hppass__dac__t.html#a9809ce5e9ab5f783a4fbcc811ce36865" title="DAC mode. ">cy_stc_hppass_dac_t::mode</a>. </p>
<ul>
<li>Buffered mode - DAC value</li>
<li>Hysteretic Buffered mode - DAC low threshold</li>
<li>Slope modes - DAC stop value</li>
<li>LUT modes - LUT stop address </li>
</ul>

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